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Introduction to EDK
The Xilinx Embedded Development Kit (EDK) is a suite of tools used to develop embedded system-on-chip designs. These designs can incorporate a wide range of soft- and hard-IP cores such as microprocessors, interconnects, memories, and an assortment of peripherals. The EDK tool suite provides a single environment for design, simulation, synthesis, and compilation.
System Design Using EDK
Embedded system design using EDK consists of two separate but interacting steps. First, the system-on-chip hardware is designed. FPGAs have a malleable fabric which can be reconfigured with any circuit, thus, hardware design consists of two sub-tasks: developing custom circuitry and building integrated systems. The first sub-task is to develop custom circuitry for use in the system-on-chip design, though this step is often unnecessary because of the plethora of existing soft-IP cores which can be used off-the-shelf. Custom circuitry is usually developed using a hardware development language such VHDL or Verilog in addition to a synthesis tool which can translate the high-level hardware description into the low-level gate logic. The Xilinx Project Navigator tool, included in the Xilinx ISE product, supports VHDL/Verilog development, VHDL/Verilog synthesis, and VHDL/Verilog simulation (through third party simulators such as ModelSim).
Once the required set of soft-IP cores has been developed, an entire system-on-chip design can be created using the Xilinx Platform Studio tool. This tool allows designers to combine all available IP cores into a single design. In typical designs this is accomplished by interconnecting all of the required IP cores using a bus architecture. A microprocessor is usually connected to the bus as well, allowing for the system-on-chip to be controlled using software programs. The end result is a programmable system-on-chip which includes a variety of soft-IP peripherals, all of which can be controlled by the software.
The second step in system-on-chip design using EDK, then, is the development of software to control the microprocessor and all of the connected peripherals. This step is as complicated or as simple as required by the system being designed. The system-on-chip hardware designed in the first step presents a low-level interface to the software. This low level interface can be programmed directly by the developer in what is often called "bare metal" programming. In this case the system programmer is responsible for correctly implementing the low level details of interacting with any given peripheral and often requires detailed knowledge of assembly programming and low-level C.
It is also possible to install an embedded operating system on the system-on-chip design. This allows the system programmer to work at a high level of abstraction and can ease the development of embedded system-on-chip designs. Embedded operating systems, however, would not support any custom circuitry developed for the system-on-chip design, though they do often include support for interacting with commodity soft-IP cores. If the embedded operating system does not support a peripheral in the system-on-chip design then it is the responsibility of the system programmer to provide support usually though developing a custom operating system driver. Thus, even when embedded operating systems are employed, knowledge of assembly and low-level C may be required.
System Implementation in EDK
Once the embedded system-on-chip design has been completed it must be translated into an implementation suitable for the FPGA's malleable fabric. Like the design phase, this phase consists of two phases. Unlike the design phase, however, the implementation process is automated using CAD tools. In the first phase of implementation, called the synthesis phase, a set of synthesis tools will translate the design from the high-level hardware description language into a gate-level description for a specific FPGA. The Xilinx development suite provides the Xilinx Synthesis Technology (XST) for soft-IP core synthesis and the Xilinx Place and Route (PAR) tool for placement and routing. When using the Xilinx development suite, during the synthesis phase the following happens in the given order:
- System-on-chip elaboration
In this step the graphical or textual high-level system-on-chip design is converted to a single VHDL design for use by the synthesis tool. This step is necessary because the system-on-chip design is done using graphical tools or human readable text files which are not directly usable by the CAD system. This step simply converts the human representation of the system-on-chip design into a well-defined computer readable format.
- Soft-IP core synthesis
In this step the XST synthesis tool will synthesis the VHDL design produced by the elaboration step. Synthesis proceeds by converting each soft-IP core in the design into a netlist, also commonly called an EDIF file. A netlist is a low-level circuit description which contains only primitive circuit instantiations and connectivity information. The netlist produced at this step is a logical description of the circuit, meaning that the netlist consists of core instantiations, FSM descriptions, adders, multipliers, shift-registers, connectivity information, etc.
- Netlist translation
This step translates the netlist produced in the synthesis step into a lower-level netlist. The translated netlist from this steps is still a logical description of the netlist except that the circuit is described in terms of boolean gates, flip-flops, RAMs, decoders, etc.
- Physical Mapping
The physical mapping step takes the low-level logical netlist description produced by the translation step and maps the logic circuit description into a physical circuit description. The netlist produced describes a physical circuit inside of a particular FPGA target. Thus, the netlist after this step is a physical description consisting of logic cells, I/O cells, and other components which physically exist inside of the target FPGA.
- Netlist placement
At this point their is a physical netlist description for each of the original soft-IP cores. In the placement step all of the physical netlists are placed into the FPGA. Placement takes into account any constraints which might be present for a netlist, connectivity between netlists, and many other things. At the end of this step all of the physical primitives described in every netlist is placed at a particular physical location within the FPGA.
- Netlist routing
Once all primitives have been placed at physical locations within the FPGA, the connectivity between communicating primitives much be established. The routing step routes wires from the outputs of one primitive to the inputs of other primitives, thus establishing a primitive communication channel between the primitive components. At the end of this step all of the communication in the original soft-IP core description is established at the physical layer within the FPGA.
- Bitstream generation
At this point all of the soft-IP cores in the system-on-chip design have been placed physically withing the FPGA and the communication between the primitive components has been established. The last step in the process is bitstream generation. In this step the physical design is converted into a bit-level description. FPGAs are based on look-up-tables (LUTs) and configurable signal routing logic which is SRAM based. Thus, by setting or clearing the correct bits inside of the FPGAs logic and routing SRAMs a particular circuit can be described physically within the FPGA. Bitstream generation determines the configuration (one or zero) or every logic or routing SRAM bit in the FPGA. At the end of this step the original system-on-chip design can be downloaded to the FPGA for execution.
In the second phase, the compilation phase, the software program which controls the system-on-chip design is compiled from the C source and assembly into the binary format used by the microprocessor. The Xilinx development suite provides an industry standard GCC software compiler suite which can compile C, C++, or assembly for all of the microprocessors which are supported. After the software has been compiled into a binary executable by GCC, the hardware and software are combined into one overall bitstream. This bitstream is used to initialize the SRAM fabric of the FPGA with the hardware design and the system-on-chip memories with the software program. Thus, when the system-on-chip is boot-strapped any microprocessors in the system will execute the software associated with them.